1. Field of the Invention
The present invention relates to a semiconductor device formed by a semiconductor chip being mounted on a package substrate, and to an electronic device including the semiconductor device.
Priority is claimed on Japanese Patent Application No. 2007-321751, filed Dec. 13, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, greater miniaturization and multi-layering of wirings have been progressing with the higher integration of semiconductor chips. On the other hand, miniaturization of the package size is required for high-density packaging of a semiconductor package (semiconductor device). For example, a semiconductor package, such as BGA (ball grid array) and CSP (chip size package), has a structure in which a semiconductor chip is mounted on a package substrate, and the semiconductor chip and the package substrate are connected using, for example, wire bonding. In this case, solder balls for external connection can be arranged at the rear surface of the package substrate. Thereby, the semiconductor package is applicable to multiple pins.
A conventional BGA-type semiconductor device mainly includes a wiring substrate (package substrate) having multiple connection pads provided on the top surface thereof and multiple lands provided on the bottom surface thereof and electrically connected to the connection pads, a semiconductor chip mounted on the top surface of the wiring substrate, wirings to electrically connect electrode pads provided on the semiconductor chip and the connection pads, a seal made of an insulating resin and covering the semiconductor chip and the wirings, and external terminals provided on the lands.
The conventional BGA-type semiconductor device is mounted on compact electronic devices, such as a cellular phone, and therefore required to withstand stress due to a difference in thermal expansion coefficients between the wiring substrate and the semiconductor chip, and mechanical impact, such as when an electronic device is dropped.
However, a solder ball 108 arranged at a corner K′ of a wiring substrate 102 is likely to fracture as shown in FIG. 9. As shown in FIG. 10, the solder ball 108 is subjected to stress from a solder resist 106 at the corner K′, and the solder ball 108 cracks in the vicinity of a land 104 on the corner K′ side since the solder ball 108 is damaged by stress caused by a difference in thermal expansion coefficients between a semiconductor chip and a wiring substrate or a resin, or by impact applied to the solder ball 108 arranged at the outermost alignment. Accordingly, connection of the solder ball 108 in the vicinity of the corner K′ is required to be strengthened to enhance the reliability of a secondary mounting of a semiconductor device. Advancement of damage depends on the structure of a semiconductor device, and therefore has directionality. Therefore, countermeasures are required.
For example, Japanese Unexamined Patent Application, Fast Publication No. 2001-230513 discloses a technique of increasing connection strength of solder balls to prevent damage or crack in the balls. Specifically, an opening of a solder resist is intentionally shifted with respect to a land having an SMD (solder mask defined) structure so that a side surface of the land is exposed to be NSMD (non-solder mask defined), and thereby the connection strength is enhanced.
However, the connection strength is enhanced to some extent, but still not enough in the technique since only the connection strength of conventional NSMD structures can be achieved by the solder resist being shifted to expose the side surface of the land. The connection strength needs to be further enhanced for products requiring greater connection strength than that of the conventional NSMD structure.